1. Field of the Invention
The embodiments disclosed herein relate to contact resistance modeling and, more particularly, to a method, a program storage device and a computer system for modeling the total contact resistance of a semiconductor device, such as a metal oxide semiconductor field effect transistor (MOSFET) or metal oxide semiconductor variable capacitor (MOS varactor), that specifically has a multi-finger gate structure.
2. Description of the Related Art
Parasitic contact resistance is one of the largest parasitic resistances that impact semiconductor device performance. Thus, during semiconductor device design, accurate modeling of the total contact resistance is very important. However, the current techniques used to model the total contact resistance of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs) or metal oxide semiconductor variable capacitors (MOS varactors), that specifically have a multi-finger gate structure may result in a relatively large error. Therefore, there is a need in the art for technique that can be used to more accurately model the total contact resistance of such devices.